NAND memory arrays

ABSTRACT

A NAND memory array has a first dielectric layer formed on a first portion of a semiconductor substrate and a second dielectric layer formed on a second portion of the semiconductor substrate and adjoining the first dielectric layer. The first dielectric layer is thicker than the second dielectric layer. A first gate stack is formed on the first dielectric layer to form a drain select gate. A string of second gate stacks is formed on the second dielectric layer to form a NAND string of floating-gate memory cells. A first end of the NAND string is coupled in series with the drain select gate. A third gate stack is formed on the second dielectric layer to form a source select gate. A second end of the NAND string is coupled in series with the source select gate.

RELATED APPLICATION

This Application is a Continuation of U.S. application Ser. No.10/920,561, titled “NAND MEMORY ARRAY AND METHODS,” filed Aug. 18, 2004(pending), which application is commonly assigned and incorporatedherein by reference.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to memory devices and inparticular the present invention relates to NAND memory arrays andmethods.

BACKGROUND OF THE INVENTION

Memory devices are typically provided as internal storage areas incomputers. The term memory identifies data storage that comes in theform of integrated circuit chips. In general, memory devices contain anarray of memory cells for storing data, and row and column decodercircuits coupled to the array of memory cells for accessing the array ofmemory cells in response to an external address.

One type of memory is a non-volatile memory known as flash memory. Aflash memory is a type of EEPROM (electrically-erasable programmableread-only memory) that can be erased and reprogrammed in blocks. Manymodern personal computers (PCs) have their BIOS stored on a flash memorychip so that it can easily be updated if necessary. Such a BIOS issometimes called a flash BIOS. Flash memory is also popular in wirelesselectronic devices because it enables the manufacturer to support newcommunication protocols as they become standardized and to provide theability to remotely upgrade the device for enhanced features.

A typical flash memory comprises a memory array that includes a largenumber of memory cells arranged in row and column fashion. Each of thememory cells includes a floating-gate field-effect transistor capable ofholding a charge. The cells are usually grouped into blocks. Each of thecells within a block can be electrically programmed on an individualbasis by charging the floating gate. The charge can be removed from thefloating gate by a block erase operation. The data in a cell isdetermined by the presence or absence of the charge on the floatinggate.

A NAND flash memory device is a common type of flash memory device, socalled for the logical form in which the basic memory cell configurationis arranged. Typically, the array of memory cells for NAND flash memorydevices is arranged such that the control gate of each memory cell of arow of the array is connected to a word-select line. Columns of thearray include strings (often termed NAND strings) of memory cellsconnected together in series, source to drain, between a pair of selectlines, a source select line and a drain select line. The source selectline includes a source select gate at each intersection between a NANDstring and the source select line, and the drain select line includes adrain select gate at each intersection between a NAND string and thedrain select line. The select gates are typically field-effecttransistors. Each source select gate is connected to a source line,while each drain select gate is connected to a column bit line.

The memory array is accessed by a row decoder activating a row of memorycells by selecting the word-select line connected to a control gate of amemory cell. In addition, the word-select lines connected to the controlgates of unselected memory cells of each string are driven to operatethe unselected memory cells of each string as pass transistors, so thatthey pass current in a manner that is unrestricted by their stored datavalues. Current then flows from the source line to the column bit linethrough each NAND string via the corresponding select gates, restrictedonly by the selected memory cells of each string. This places thecurrent-encoded data values of the row of selected memory cells on thecolumn bit lines.

To prevent programming of unselected strings while selected strings arebeing programmed, the voltage level of the unselected strings isincreased. However, current leakage (often referred to as gate-induceddrain leakage or GIDL) through the drain select gates acts to reduce theincreased voltage level of the unselected strings that can causeinadvertent programming of these strings and can reduce programmingspeeds.

For the reasons stated above, and for other reasons stated below whichwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art forreducing current leakage from drain select gates of unselected NANDstrings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified block diagram of a memory system, according to anembodiment of the invention.

FIG. 2 is a schematic of a NAND memory array in accordance with anotherembodiment of the invention.

FIGS. 3A-3F are cross-sectional views of a portion of a memory arrayduring various stages of fabrication, according to another embodiment ofthe invention.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference ismade to the accompanying drawings that form a part hereof, and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention. The term wafer orsubstrate used in the following description includes any basesemiconductor structure. Both are to be understood as includingsilicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI)technology, thin film transistor (TFT) technology, doped and undopedsemiconductors, epitaxial layers of a silicon supported by a basesemiconductor structure, as well as other semiconductor structures wellknown to one skilled in the art. Furthermore, when reference is made toa wafer or substrate in the following description, previous processsteps may have been utilized to form regions/junctions in the basesemiconductor structure, and terms wafer or substrate include theunderlying layers containing such regions/junctions. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims and equivalents thereof.

FIG. 1 is a simplified block diagram of a memory system 100, accordingto an embodiment of the invention. Memory system 100 includes anintegrated circuit flash memory device 102, e.g., a NAND memory device,that includes an array of flash memory cells 104, an address decoder106, row access circuitry 108, column access circuitry 110, controlcircuitry 112, Input/Output (I/O) circuitry 114, and an address buffer116. Memory system 100 includes an external microprocessor 120, ormemory controller, electrically connected to memory device 102 formemory accessing as part of an electronic system.

The memory device 102 receives control signals from the processor 120over a control link 122. The memory cells are used to store data thatare accessed via a data (DQ) link 124. Address signals are received viaan address link 126 that are decoded at address decoder 106 to accessthe memory array 104. Address buffer circuit 116 latches the addresssignals. The memory cells are accessed in response to the controlsignals and the address signals. It will be appreciated by those skilledin the art that additional circuitry and control signals can beprovided, and that the memory device of FIG. 1 has been simplified tohelp focus on the invention.

FIG. 2 is a schematic of a NAND memory array 200 as a portion of memoryarray 104 in accordance with another embodiment of the invention. Asshown in FIG. 2, the memory array 200 includes word lines 202 ₁ to 202_(N) and intersecting local bit lines 204 ₁ to 204 _(M). For ease ofaddressing in the digital environment, the number of word lines 202 andthe number of bit lines 204 are each some power of two, e.g., 256 wordlines 202 by 4,096 bit lines 204. The local bit lines 204 are coupled toglobal bit lines (not shown) in a many-to-one relationship.

Memory array 200 includes NAND strings 206 ₁ to 206 _(M). Each NANDstring includes floating-gate transistors 208 ₁ to 208 _(N), eachlocated at an intersection of a word line 202 and a local bit line 204.The floating-gate transistors 208 represent non-volatile memory cellsfor storage of data. The floating-gate transistors 208 of each NANDstring 206 are connected in series source to drain between a sourceselect line 214 and a drain select line 215. Source select line 214includes a source select gate 210, e.g., a field-effect transistor(FET), at each intersection between a NAND string 206 and source selectline 214, and drain select line 215 includes a drain select gate 212,e.g., a field-effect transistor (FET), at each intersection between aNAND string 206 and drain select line 215. In this way, thefloating-gate transistors 208 of each NAND string 206 are connectedbetween a source select gate 210 and a drain select gate 212.

A source of each source select gate 210 is connected to a common sourceline 216. The drain of each source select gate 210 is connected to thesource of the first floating-gate transistor 208 of the correspondingNAND string 206. For example, the drain of source select gate 210 ₁ isconnected to the source of floating-gate transistor 208 ₁ of thecorresponding NAND string 206 ₁. Each source select gate 210 includes acontrol gate 220.

The drain of each drain select gate 212 is connected to the local bitline 204 for the corresponding NAND string at a drain contact 228. Forexample, the drain of drain select gate 212 ₁ is connected to the localbit line 204 ₁ for the corresponding NAND string 206 ₁ at drain contact228 ₁. The source of each drain select gate 212 is connected to thedrain of the last floating-gate transistor 208 _(N) of the correspondingNAND string 206. For example, the source of drain select gate 212 ₁ isconnected to the drain of floating-gate transistor 208 _(N) of thecorresponding NAND string 206 ₁.

Typical construction of floating-gate transistors 208 includes a source230 and a drain 232, a floating gate 234, and a control gate 236, asshown in FIG. 2. Floating-gate transistors 208 have their control gates236 coupled to a word line 202. A column of memory array 200 includes aNAND string 206 and the source and drain select gates connected thereto.A row of the floating-gate transistors 208 are those transistorscommonly coupled to a given word line 202.

FIGS. 3A-3F are cross-sectional views of a portion of a memory array,such as a portion of the memory array 200 of FIG. 2, during variousstages of fabrication, according to another embodiment of the invention.In FIG. 3A a first dielectric layer 302, e.g., an oxide layer, isformed, e.g., blanket deposited or thermally grown, on a semiconductorsubstrate 300 that is of monocrystalline silicon or the like. A hardmask layer 304 is formed on the first dielectric layer 302. The hardmask layer 304 can be a second dielectric layer, such as a nitridelayer, e.g., a silicon nitride (Si₃N₄) layer, that is blanket depositedon the first dielectric layer 302. Hard mask layer 304 is patterned andportions thereof are removed, e.g., by dry etching, in regions 310 whereNAND strings of memory cells, such as floating gate memory cells, e.g.,floating-gate transistors, will be formed, as shown in FIG. 3B. For oneembodiment, the first dielectric layer 302 is removed from regions 310to expose portions 312 of substrate 300 in regions 310, as shown in FIG.3B. For one embodiment, a selective dry etch that stops at substrate 300accomplishes this.

A third dielectric layer 314, e.g., an oxide layer, is formed, e.g.,thermally grown, on the exposed portions 312 of substrate 300 in FIG.3C. The third dielectric layer 314 is subsequently nitridized. For oneembodiment, nitridation is performed by exposing the third dielectriclayer 314 to a nitrogen-containing environment, e.g., an environmentcontaining NO, N₂O, NH₃, etc. at an elevated temperature, in FIG. 3D.The remaining portion of hard mask layer 304 is removed in FIG. 3E.

The resulting structure of FIG. 3E includes the first dielectric layer(or gate dielectric layer) 302 in a region 320 where drain select gateswill be formed and the third dielectric layer (or tunnel dielectriclayer) 314 in the regions 310 where the NAND strings will be formed.Note that the first dielectric layer 302 in region 320 can be thickerthan the third dielectric layer 314 in the regions 310. The thickerfirst dielectric layer 302 acts to reduce gate-induced drain leakage orGIDL through the drain select gates. Note further that hard mask layer304 prevents nitridation of first dielectric layer 302, wherenitridation may negatively affect performance of the drain select gatesand is not desired, but allows nitridation of third dielectric layer314, where the nitridation acts to improve reliability of the memorycells.

FIG. 3F illustrates gate stacks 322 and 324 formed on the firstdielectric layer 302 and gate stacks 326 and 328 formed on the thirddielectric layer 314. Note that FIG. 3F has been enlarged for clarity.Gate stacks 322 and 324 and the first dielectric layer 302 form drainselect gates 323 and 325, e.g., field effect transistors (FETs), wherethe first dielectric layer 302 acts as a gate dielectric layer of drainselect gates 323 and 325. Gate stacks 326 and the third dielectric layer314 form floating-gate memory cells 327, such as floating-gatetransistors, and gate stacks 328 and the third dielectric layer 314 formfloating-gate memory cells 329, such as floating-gate transistors, wherethe third dielectric layer 314 acts as a tunnel dielectric layer formemory cells 327 and 329. Gate stacks 330 and 332 are also formed on thethird dielectric layer 314. Gate stacks 330 and 332 and the thirddielectric layer 314 form source select gates 331 and 333, e.g., fieldeffect transistors (FETs), where the third dielectric layer 314 acts asa gate dielectric layer of source select gates 331 and 333. It will beapparent that the process could be readily modified to form a sourceselect gates 331 and 333 on portions of the first dielectric layer 302similar to drain select gates 323 and 325 if desired.

Memory cells 327 are connected in series, source to drain, between drainselect gate 323 and source select gate 331 to form a NAND string 334between drain select gate 323 and source select gate 331. Memory cells329 are connected in series, source to drain, between drain select gate325 and source select gate 333 to form a NAND string 335 between drainselect gate 325 and source select gate 333. For one embodiment,source/drain regions 336 are formed in substrate 300. For anotherembodiment, successive memory cells of the respective NAND strings sharea source/drain region 336, drain select gate 323 and memory cell 327 ₁of NAND string 334 share a source/drain region 336, source select gate331 and memory cell 327 _(K) of NAND string 334 of NAND string 334 sharea source/drain region 336, drain select gate 325 and memory cell 329 ₁of NAND string 335 share a source/drain region 336, and source selectgate 333 and memory cell 329 _(L) of NAND string 335 share asource/drain region 336.

Each of gate stacks 323 and 325 include a first conductive layer 338,such as a conductively doped polysilicon layer, formed on the firstdielectric layer 302, a fourth dielectric layer 340 formed on the firstconductive layer 338, and a second conductive layer 350 formed on thefourth dielectric layer 340. Each of gate stacks 326, 328, 330, and 332include the first conductive layer 338 formed on the third dielectriclayer 314, the fourth dielectric layer 340 formed on the firstconductive layer 338, and the second conductive layer 350 formed on thefourth dielectric layer 340.

For one embodiment, the second conductive layer 350 is a conductivelydoped polysilicon layer or a metal or metal-containing layer, such as arefractory metal or refractory metal silicide layer. The metals ofchromium (Cr), cobalt (Co), hafnium (Hf), molybdenum (Mo), niobium (Nb),tantalum (Ta), titanium (Ti), tungsten (W), vanadium(V) and zirconium(Zr) are generally recognized as refractory metals. For anotherembodiment, the second conductive layer 350 may be a single conductivelayer of one or more conductive materials, e.g., metal ormetal-containing materials, or two or more conductive layers, such as ametal or metal-containing layer formed on a conductively dopedpolysilicon layer. For one embodiment, the fourth dielectric layer 340may be an oxide layer, a nitride layer, an oxide-nitride-oxide (ONO)layer, etc.

For each of the memory cells 327 and 329, the second conductive layer350 is a control gate (or a word line, such as a word line 202 of FIG.2), the first conductive layer 338 is a floating gate, and the fourthdielectric layer interposed between the first conductive layer 338 andthe second conductive layer 350 is an intergate dielectric layer. Foreach of the drain select gates 323 and 325 and the source select gates331 and 333, for some embodiments, the first conductive layer 338 andthe second conductive layer 350 may be strapped (or shorted) together sothat the shorted together first conductive layer 338 and secondconductive layer 350 form a control gate of the respective select gates,where the control gate of each of the source select gates 331 and 333 isa source select line, such as a source select line 214 of FIG. 2, andthe control gate of each of the drain select gates 323 and 325 is adrain select line, such as a drain select line 215 of FIG. 2. Foranother embodiment, the first conductive layer 338 and the secondconductive layer 350 are not shorted together, and first conductivelayer 338 forms the control gate of the respective select gates.

Formation of gate stacks 322, 324, 326, 328, 330, and 332 is well knownand will not be detailed herein. Generally, the first conductive layer338 is formed on the first dielectric layer 302 and the third dielectriclayer 314. After the first conductive layer 338 is formed, it ispatterned parallel to the plane of FIG. 3F. The fourth dielectric layer340 is then formed on the first conductive layer 338, and the secondconductive layer 350 is formed on the fourth dielectric layer 340. Thesecond conductive layer 350 is patterned orthogonally to the patterningof the first conductive layer 338, and the second conductive layer 350,the fourth dielectric layer 340, and the first conductive layer 338 areremoved, e.g., by selective etching that stops at the first dielectriclayer 302 and the third dielectric layer 314, to expose portions of thefirst dielectric layer 302 between gate stacks 322 and 324, between gatestacks 322 and 326 ₁, and between gate stacks 324 and 328 ₁. This alsoexposes portions of the third dielectric layer 314 between gate stacks322 and 326 ₁, between gate stacks 324 and 328 ₁, between gate stacks330 and 326 _(K), between gate stacks 332 and 328 _(L), and betweensuccessive gate stacks 326 and successive gate stacks 328.

It is generally desirable to use the same processing for all of the gatestacks and to short the first and second conductive layers of the gatestacks of the drain and source select gates together, as describedabove. However, since the select gates function differently than thememory cells, the gate stacks of the select gates can be formedindependently of the gate stacks of the memory cells.

CONCLUSION

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe invention will be apparent to those of ordinary skill in the art.Accordingly, this application is intended to cover any adaptations orvariations of the invention. It is manifestly intended that thisinvention be limited only by the following claims and equivalentsthereof.

1. A NAND memory array, comprising: at least one NAND string of floatinggate memory cells comprising: a first dielectric layer formed on a firstportion of a semiconductor substrate; a second dielectric layer formedon a second portion of the semiconductor substrate and adjoining thefirst dielectric layer, wherein the first dielectric layer is thickerthan the second dielectric layer; a first gate stack formed on the firstdielectric layer to form a drain select gate; a string of second gatestacks formed on the second dielectric layer to form the at least oneNAND string of floating-gate memory cells, a first end of the at leastone NAND string coupled in series with the drain select gate; and athird gate stack formed on the second dielectric layer to form a sourceselect gate, a second end of the at least one NAND string coupled inseries with the source select gate.
 2. The NAND memory array of claim 1,wherein the source and drain select gates and the at least one NANDstring form a column of the memory array.
 3. The NAND memory array ofclaim 1, wherein the drain select gate and a first memory cell at thefirst end of the at least one NAND string share a first source/drainregion formed in the substrate and the source select gate and a secondmemory cell at the second end of the at least one NAND string share asecond source/drain region formed in the substrate.
 4. The NAND memoryarray of claim 1, wherein the drain select gate further comprises adrain select line formed on the first dielectric layer, the sourceselect gate further comprises a source select line formed on the seconddielectric layer, and each of the memory cells further comprises afloating gate formed on the second dielectric layer, an intergatedielectric layer formed on the floating gate, and a word line formed onthe intergate dielectric layer.
 5. The NAND memory array of claim 1,wherein each of the memory cells and the select gate further comprise afirst conductive layer formed on the second dielectric layer, a thirddielectric layer formed on the first conductive layer, and a secondconductive layer formed on the third dielectric layer, and wherein thedrain select gate comprises the first conductive layer formed on thefirst dielectric layer, the third dielectric layer formed on the firstconductive layer, and the second conductive layer formed on the thirddielectric layer.
 6. The NAND memory array of claim 5, wherein the firstconductive layer is a polysilicon layer.
 7. The NAND memory array ofclaim 6, wherein the polysilicon layer is conductively doped.
 8. TheNAND memory array of claim 5, wherein the second conductive layer isselected from the group consisting of a polysilicon layer, a metallayer, a metal-containing layer, a layer containing one or moreconductive materials, and one or more conductive layers.
 9. The NANDmemory array of claim 5, wherein the third dielectric layer comprisesone or more layers of dielectric material.
 10. The NAND memory array ofclaim 1, wherein each of the first and second dielectric layers areoxide layers.
 11. The NAND memory array of claim 1, wherein the seconddielectric layer is nitrided.
 12. A NAND memory array comprising: aplurality of rows of memory cells; and a plurality of columns of NANDstrings of memory cells, each NAND string selectively connected to a bitline through a drain select gate of the respective column; wherein eachof the drain select gates comprises a first dielectric layer formed on asemiconductor substrate of the memory array and a control gate formed onthe first dielectric layer; and wherein each of the memory cells of eachof the NAND strings comprises a second dielectric layer formed on thesubstrate laterally of the first dielectric layer and adjoining thefirst dielectric layer, a floating gate formed on the second dielectriclayer, a third dielectric layer formed on the floating gate, and acontrol gate formed on the third dielectric layer, wherein the firstdielectric layer is thicker than the second dielectric layer.
 13. TheNAND memory array of claim 12, wherein the first and second dielectriclayers are thermal oxide layers.
 14. The NAND memory array of claim 12,wherein the second dielectric layer is a nitride-containing thermaloxide layer.
 15. A memory device, comprising: a memory array,comprising: a plurality of rows of memory cells, the rows respectivelyconnected to corresponding word lines; and a plurality of columns, therespective columns comprising a NAND string of memory cells connectedbetween a source select gate and a drain select gate, each drain selectgate selectively coupling the NAND string connected thereto to a bitline; wherein each drain select gate comprises a first gate stack formedon a first dielectric layer formed on a substrate; wherein each of thememory cells of each of the NAND strings comprises a second gate stackformed on a second dielectric layer formed on the substrate laterally ofthe first dielectric layer and adjoining the first dielectric layer; andwherein each source select gate comprises a third gate stack formed onthe second dielectric layer; and column access circuitry connected tothe bit lines; and row access circuitry connected to the word lines. 16.The memory device of claim 15, wherein the first gate stack comprises adrain select line formed on the first dielectric layer, the third gatestack comprises a source select line formed on the second dielectriclayer, and the second gate stack comprises a floating gate formed on thesecond dielectric layer, an intergate dielectric layer formed on thefloating gate, and a control gate formed on the intergate dielectriclayer and connected to a word line.
 17. The memory device of claim 15,wherein the first and second dielectric layers are thermal oxide layers.18. The memory device of claim 15, wherein the second dielectric layeris a nitride-containing thermal oxide layer.
 19. An electronic system,comprising: a processor; and at least one memory device coupled to theprocessor, the at least one memory device comprising: a memory array,comprising: a plurality of rows of memory cells, the rows respectivelyconnected to corresponding word lines; and a plurality of columns, therespective columns comprising a NAND string of memory cells connectedbetween a source select gate and a drain select gate, each drain selectgate selectively coupling the NAND string connected thereto to a bitline; wherein each drain select gate comprises a first gate stack formedon a first dielectric layer formed on a substrate; wherein each of thememory cells of each of the NAND strings comprises a second gate stackformed on a second dielectric layer formed on the substrate laterally ofthe first dielectric layer and adjoining the first dielectric layer; andwherein each source select gate comprises a third gate stack formed onthe second dielectric layer; and column access circuitry connected tothe bit lines; and row access circuitry connected to the word lines. 20.An electronic system, comprising: a processor; and at least one memorydevice coupled to the processor, the at least one memory devicecomprising: a memory array, comprising: a plurality of rows of memorycells; and a plurality of columns of NAND strings of memory cells, eachNAND string selectively connected to a bit line through a drain selectgate of the respective column; wherein each of the drain select gatescomprises a first dielectric layer formed on a semiconductor substrateof the memory array and a control gate formed on the first dielectriclayer; and wherein each of the memory cells of each of the NAND stringscomprises a second dielectric layer formed on the substrate laterally ofthe first dielectric layer and adjoining the first dielectric layer, afloating gate formed on the second dielectric layer, a third dielectriclayer formed on the floating gate, and a control gate formed on thethird dielectric layer, wherein the first dielectric layer is thickerthan the second dielectric layer.